1. Field of the Invention
The invention relates in general to a memory, and more particularly to a resistive memory and an associated operation method.
2. Description of the Related Art
FIG. 14 shows a schematic diagram of programming a conventional resistive memory. FIG. 15 shows a schematic diagram of erasing a conventional resistive memory. A fundamental structure of a conventional resistive memory 3 is formed by a transistor T and a resistive memory cell Rcell. The resistive memory 3 is a metal/insulation layer/metal (MIM) structure. By changing the resistance of the resistive memory cell Rcell, the resistive memory 3 performs programming and erasing operations.
As shown in FIG. 14, when programming the resistive memory cell Rcell, a bias voltage +V is applied to the gate of the transistor T and the resistive memory cell Rcell, and the source of the transistor T is grounded. (i.e., coupled to 0V), such that the transistor T is turned on. A programming current Ip flows from the resistive memory cell Rcell to the transistor T. That is, the programming current Ip flows from the drain of the transistor T to the source of the transistor T.
As shown in FIG. 15, when the resistive memory cell Rcell is erased, a bias voltage +V is applied to the gate of the transistor T and the source of the transistor T, and the resistive memory cell Rcell is grounded, such that the transistor T is turned on. An erasing current Ir flows from the transistor T to the resistive memory cell Rcell. That is, the erasing current Ir flows from the source of the transistor T to the drain of the transistor T. However, when erasing a conventional resistive memory, a body effect of a transistor causes an erasing current Ir to drop, which affects operation efficiency of the conventional resistive memory and may easily lead to an erase failure.